With the size of the characteristic dimension of very large scale integrated circuits continuing to shrink, new problems have arisen in the fields of material technology, device theories, device structure and fabrication process, etc. To solve these new problems, researchers adopt a series of new technologies. SOI means silicon on insulator. In SOI technique, device is fabricated in a very thin silicon film, and the device and substrate are separated by a buried oxide layer. This structure makes SOI have many advantages over bulk silicon technique. Small parasitic capacitance enable the high speed and low power consumption of the SOI device. Full dialectical isolation feature of SOI CMOS entirely eliminates the parasitic latch-up effect of bulk silicon CMOS device, and improve the integration density and the ability to resist radiation. SOI technique is widely used for RF, high voltage, and anti-radiation field and so on.
SOI MOS is divided into a partially depleted SOI MOS (PDSOI) and a fully depleted SOI MOS (FDSOI) according to whether the body region of the active area is fully depleted or not. In general, the top silicon film of the FDSOI is very thin. Thin film SOI silicon costs high and the threshold voltage of the FDSOI is hardly controlled. Therefore, the PDSOI is commonly used.
The body region of the active area of PDSOI is not fully depleted, so that the body region is suspended. The charge due to an impact ionization mechanism can not be transferred quickly, which will result in the floating body effect. As for the electrons-hole pairs created from the impact mechanism of the NMOS channel electrons, the holes migrate towards the body region. The floating effects will result in the holes accumulation and raised body region electric potential, and thus give rise to a decrease of the threshold voltage of SOI NMOS and a increase of the leakage current, resulting in a warping phenomenon of the device output characteristic curves IdVd, which is called Kink effect. Kink effect has many adverse effects to the performance and reliability of the device and circuit, so that the kink effect should be suppressed in the design of the device. For SOI PMOS, the electrons-hole pairs created from the impact mechanism is much less than that generated in SOI NMOS because of a lower holes ionization rate in SOI PMOS. Therefore, the Kink effect in the SOI PMOS is not obvious.
To solve the problem of partially depleting SOI NMOS, the body contact technology is widely adopted, in which the “body” contacts fixed electric potential (source or ground). FIGS. 1a-1b show traditional body contact using a T-shaped gate. At one side of the T-shaped gate, a P+ implanted region is formed and connected with the P-type body region under the gate. When the MOS device operates, charge carriers accumulated in the body region emits through the P+ channel so as to reduce the electric potential of the body region. Such a process, however, is complicated, and aggravates the parasitic effect, thus affecting partial electrical properties and enlarging the area.
Given the above, there is a need for a new body contact structure which can effectively suppress the floating body effect in the PD SOI device without enlarging the chip area, which is simple and compatible to the process of fabricating the integrated circuits.